CellPerformance
All things related to getting the best performance from your Cell Broadband Engine™ (CBE) processor.
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Articles
Cross-compiling for PS3 Linux
n this article, I will detail the basic steps I used to get started building on a host PC and running on the PS3.

Unaligned scalar load and store on the SPU
An example of unaligned loads and stores on the SPU. The solution to this problem is to remember that the SPU does not have a scalar instruction set or access local memory in anything except 16 bytes quadwords.

atan2 on SPU
A branch-free implementation of atan2 vector floats for the SPU.

Branch-free implementation of half-precision (16 bit) floating point
The goal of this project is serve as an example of developing some relatively complex operations completely without branches - a software implementation of half-precision floating point numbers.

Better Performance Through Branch Elimination
An introduction to branch penalties: Why it's a good idea to avoid branchy code.

Box Overlap
A look at a function to test for overlap between 3D boxes, and how to optimize it for the CBE.

A 4x4 Matrix Inverse
Study case about how to convert scalar code indo SIMD code for PPU and SPU using the matrix inverse as example.

Avoiding Microcoded Instructions On The PPU
Executing instructions from microcode can wreck havok on inner loop performance. Find out which instructions are microcoded and how to avoid them.

Choosing to Avoid Branches: A Small Altivec Example
An example of why less instructions doesn't always equal faster code.

More Techniques for Eliminating Branches
Some additional examples for eliminating integer and floating-point branches.

Programming with Branches, Patterns and Tips
GCC follows some straightforward rules that are useful to know when programming with branches.

Benefits to Branch Elimination
The fundamental principal behind branch elimination is that expressing a value as a simple function of its inputs (a single basic block) is often more efficient than selecting a result through a change in control flow (branching).

Background on Branching
A background in understanding how branches operate on the PPU and SPU.

Links
No Insider Info!
Although discussions on applying the Cell processor to game development are welcome here, do not ask for insider information related to Sony's Playstation 3.

The details of the hardware and development are covered by a non-disclosure agreement and under no conditions will confidential information be permitted on this site.

Playstation 3 developers are welcome to participate in the discussions but be aware that this is a publicly accessable site and information not available to the general public may not be disclosed.

Keep it clean so that we can continue to build on the community of Cell developers both inside and outside video game development.

Thank you for your cooperation,
Mike.
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Announcement: 1st International Symposium on CELL Computing (CCS 2006)
Mike Acton
June 20, 2006
The 1st International Symposium on CELL Computing (CCS 2006) will be held this year during SIGGRAPH 2006, July 27-29 in Boston, MA. Presentations and papers will be delivered by IBM and Sony in addition to video game, film and other high-performance industry experts.

Yahya H. Mirza, the founder of Aurora Borealis Software LLC is organizing the event. "For the last five years, Yahya has been the organizer of the Language Runtimes (LaR) workshop series held at the OOPSLA and Supercomputing conferences."

DESCRIPTION: (From: Aurora Borealis Software LLC)

The goal of CCS-06 is to create an environment, which fosters creativity and collaborative discussion with an explicit focus on bringing together senior industry product architects, scientists, and academic researchers to discuss in a relaxed setting how the CELL processor architecture, can be effectively utilized. CCS-06 seeks to enable innovation by helping to provide attendees with an intuitive holistic understanding of how multicore processor architectures can be leveraged. CCS-06 will seek to emphasize the inter-relationships between parallel algorithm decomposition, how the host compiler emits code, and how the emitted code is mapped to the underlying CELL processor architecture. Our aim is to aid the language designers, other parallel programming model architects, as well as the users of their respective languages by providing a venue where researchers can gain a clear understanding of the technologies discussed. Since our goal is to foster dialog and discussion, we will attempt a balance, by minimizing formality while providing enough structure to provide a useful environment.
CONFERENCE OVERVIEW [aurorasoft.net]
TOPICS OF INTEREST: (From: Aurora Borealis Software LLC)

* Programming models unifying local, in-process, and remote communication.
* New languages, language constructs and programming models for leveraging the CELL.
* New libraries, and tools for the CELL.
* Design techniques for factoring multicore algorithms.
* Numerical methods for the CELL.
* SIMD, software managed cache and thread programming optimizations.
* Intrinsic based AltiVec / SIMD programming techniques.
* Experience reports in targeting game / high quality rendering engines to the CELL.
* Applications perspective for leveraging next generation processor architectures.
* Experience reports on building CELL based clusters and other peer-to-peer distributed systems.
REGISTER NOW [aurorasoft.net] for the 1st International Symposium on CELL Computing (CCS 2006)